lhzci

Load Halfword and Zero Caching Inhibited

lhzci RT, RA, RB

Loads a halfword bypassing the cache.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

886

21:30

/

31

 

Format X-form

Opcode 0x7C0006EA

Extension Base

Operands

• RT
  Target
• RA
  Base
• RB
  Index

Example

lhzci r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads an unsigned halfword (16 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is used for memory-mapped I/O. No condition registers are affected.

Operation

EA ← (RA) + (RB); RT ← 0x000000000000ZZZZ where ZZZZ = [EA]