lhzci

Load Halfword and Zero Caching Inhibited

lhzci RT, RA, RB

Loads a halfword bypassing the cache.

Details

The Load Halfword and Zero Caching Inhibited instruction loads a halfword bypassing the cache.

Pseudocode Operation

r3 <- Memory[address]

Example

lhzci r3, r4, r5

Encoding

Binary Layout

31

0

RT

6

RA

11

RB

16

886

21

/

31

Format X-form

Opcode 0x7C0006EA

Extension Base

Operands

RT
Target
RA
Base
RB
Index