lhzci

Load Halfword and Zero Caching Inhibited

lhzci RT, RA, RB

Loads a halfword bypassing the cache.

Details

Loads an unsigned halfword (16 bits) from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache and is used for memory-mapped I/O. No condition registers are affected.

Pseudocode Operation

EA ← (RA) + (RB); RT ← 0x000000000000ZZZZ where ZZZZ = [EA]

Example

lhzci r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
886
21
/
31
 
Format X-form
Opcode 0x7C0006EA
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index