pstq

Prefixed Store Quadword

pstq RSp, D(RA), R

Stores 128 bits from two GPRs using a 34-bit offset.

Details

The Prefixed Store Quadword instruction (pstq) stores a quadword from registers RSp and RSp+1 into memory at an effective address calculated based on the base register RA, displacement d0||d1, and the current instruction address CIA. The effective address is determined by whether the prefix field R is 0 or 1. In Big-Endian byte ordering, the data is stored directly; in Little-Endian byte ordering, the data is byte-reversed before storage.

Pseudocode Operation

if 'stq' then
    EA ← (RA|0) + EXTS64(DS||0b00)
if 'pstq' & R=0 then
    EA ← (RA|0) + EXTS64(d0||d1)
if 'pstq' & R=1 then
    EA ← CIA + EXTS64(d0||d1)
if Big-Endian byte ordering then
    MEM(EA,16) ← (RSp)||(RSp+1)
if 'stq' and Little-Endian byte ordering then
    MEM(EA,16) ← (RSp)||(RSp+1)
if 'pstq' and Little-Endian byte ordering then
    MEM(EA,16) ← (RSp+1)||(RSp)

Programming Note

The pstq instruction is used to store a quadword from registers RSp and RSp+1 into memory. It calculates the effective address based on the base register RA, displacement, and current instruction address CIA, depending on the prefix field R. Ensure proper alignment for optimal performance and be aware of byte ordering differences between Big-Endian and Little-Endian systems.

Example

pstq r4, 0(r4), 0

Encoding

Binary Layout
1
0
2
6
R
8
0
9
D0
14
60
32
RS
38
RA
43
D1
48
 
Format MLS:D-form
Opcode 0x06000000
Extension Prefixed
Registers Altered CIA

Operands

  • RSp
    Src Pair
  • D
    Offset
  • RA
    Base
  • R
    PC-Rel