pstq

Prefixed Store Quadword

pstq RSp, D(RA), R

Stores 128 bits from two GPRs using a 34-bit offset.

Encoding

Binary Layout

1

0:5

2

6:7

R

8

0

9:13

D0

14:31

60

32:37

RS

38:42

RA

43:47

D1

48:63

 

Format MLS:D-form

Opcode 0x04000000F0000000

Extension Prefixed

Operands

• RSp
  Src Pair
• D
  Offset
• RA
  Base
• R
  PC-Rel

Example

pstq r4, 0(r4), 0

Registers Altered

CIA

Related

More in Prefixed

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Prefixed store of 128 bits from two consecutive general-purpose registers (RS and RS+1) to memory using a 34-bit signed offset. The effective address is computed as RA + D (if R=0) or the prefixed address. This is a prefixed instruction requiring the Prefixed extension; no condition register or status flags are affected.

Operation

if RA = 0 then
  EA ← D
else
  EA ← (RA) + D
[EA] ← RS
[EA+8] ← RS+1

Programming Note

The pstq instruction is used to store a quadword from registers RSp and RSp+1 into memory. It calculates the effective address based on the base register RA, displacement, and current instruction address CIA, depending on the prefix field R. Ensure proper alignment for optimal performance and be aware of byte ordering differences between Big-Endian and Little-Endian systems.