xsadddp

VSX Scalar Add Double-Precision

xsadddp XT, XA, XB

Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.

Encoding

Binary Layout

T

6:10

A

11:15

B

16:20

32

21:28

AX

29

BX

30

TX

31

 

Format XX3-form

Opcode 0xF0000100

Extension VSX

Operands

• XT
  Target
• XA
  Source A
• XB
  Source B

Example

xsadddp 0, 1, 2

// Scalar float add using Vector unit.

Registers Altered

FPSCR, VXSNAN, VXISI, OX, UX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds two double-precision floating-point scalar values held in the least-significant 64 bits of VSX registers XA and XB. The result is placed in the least-significant 64 bits of XT; the high 64 bits of XT are unchanged. Floating-point exceptions and FPSCR flags (VX, OX, UX, etc.) are updated according to the result and rounding mode.

Operation

XT[0:63] ← unchanged
XT[64:127] ← XA[64:127] + XB[64:127]
FPSCR ← updated based on operation and rounding

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.