xsadddp

VSX Scalar Add Double-Precision

xsadddp XT, XA, XB

Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.

Details

The xsadddp instruction adds the contents of doubleword element 0 of VSR[XA] (src1) to doubleword element 0 of VSR[XB] (src2), producing a sum with unbounded range and precision. The sum is normalized and rounded to double-precision using the rounding mode specified by RN.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP64(VSR[VRA+32].dword[0])
src2 ← bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
v ← bfp_ADD(src1, src2)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsadddp 0, 1, 2

Encoding

Binary Layout
T
0
A
6
B
11
32
16
AX
21
BX
29
TX
30
 
Format XX3-form
Opcode 0xF0000020
Extension VSX
Registers Altered FPSCR, VXSNAN, VXISI, OX, UX

Operands

  • XT
    Target
  • XA
    Source A
  • XB
    Source B
  • %XT
    Target Vector-Scalar Register
  • %XA
    Source Vector-Scalar Register
  • %XB
    Source Vector-Scalar Register