xsadddp

VSX Scalar Add Double-Precision

xsadddp XT, XA, XB

Adds two double-precision floating-point values from vector scalar registers and stores the result in a target vector scalar register.

Details

Adds two double-precision floating-point scalar values held in the least-significant 64 bits of VSX registers XA and XB. The result is placed in the least-significant 64 bits of XT; the high 64 bits of XT are unchanged. Floating-point exceptions and FPSCR flags (VX, OX, UX, etc.) are updated according to the result and rounding mode.

Pseudocode Operation

XT[0:63] ← unchanged
XT[64:127] ← XA[64:127] + XB[64:127]
FPSCR ← updated based on operation and rounding

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsadddp 0, 1, 2

// Scalar float add using Vector unit.

Encoding

Binary Layout
T
0
A
6
B
11
32
16
AX
21
BX
29
TX
30
 
Format XX3-form
Opcode 0xF0000100
Extension VSX
Registers Altered FPSCR, VXSNAN, VXISI, OX, UX

Operands

  • XT
    Target
  • XA
    Source A
  • XB
    Source B
  • %XT
    Target Vector-Scalar Register
  • %XA
    Source Vector-Scalar Register
  • %XB
    Source Vector-Scalar Register