plxvp

Prefixed Load VSX Vector Pair

plxvp XT, D(RA), R

Loads a 256-bit vector pair with 34-bit offset.

Details

Loads a 256-bit (32-byte) vector pair from memory using a 34-bit signed offset encoded as a 8-byte prefix + suffix. When R=0, the offset is relative to RA; when R=1, the offset is relative to the current instruction address. Requires VSX and Prefixed instruction support.

Pseudocode Operation

D ← EXTS(D0 || D1); EA ← (R=0 ? (RA) : NIA) + D; XT ← [EA]; (XT+1) ← [EA+16]

Programming Note

The plxvp instruction is used to load a pair of VSX vectors from memory into the VSRs. Ensure that the number of bytes specified in GPR[RB] does not exceed 16, as it will be clamped if it does. This instruction requires the VSX or Vector facility to be enabled in the MSR register, depending on the SX bit setting.

Example

plxvp vs1, 0(r4), 0

Encoding

Binary Layout
1
0
2
6
R
8
0
9
D0
14
58
32
XT
38
RA
43
D1
48
 
Format 8LS:D-form
Opcode 0x04000000E8000000
Extension Prefixed
Registers Altered MSR

Operands

  • XT
    Target
  • D
    Offset
  • RA
    Base
  • R
    PC-Rel