plxvp

Prefixed Load VSX Vector Pair

plxvp XT, D(RA), R

Loads a 256-bit vector pair with 34-bit offset.

Details

The plxvp instruction is used to load a pair of VSX (Vector Scalar Extension) vectors from memory into the VSRs (Vector-Scalar Registers). The data is loaded in Big-Endian byte ordering, and the effective address is determined by the contents of GPR[RA] or 0 if RA is 0. The number of bytes to load is specified by the lower 8 bits of GPR[RB]. If the number of bytes exceeds 16, it is clamped to 16.

Pseudocode Operation

if SX=0 & MSR.VSX=0 then VSX_Unavailable()
if SX=1 & MSR.VEC=0 then Vector_Unavailable()
EA ←(RA=0) ? 0 : GPR[RA]
nb ←EXTZ(GPR[RB].bit[0:7])
if nb>16 then nb ←16
if nb>0 then do i = 0 to nb-1
    VSR[32×SX+S].byte[i] ← MEM(EA+i,1)
end

Programming Note

The plxvp instruction is used to load a pair of VSX vectors from memory into the VSRs. Ensure that the number of bytes specified in GPR[RB] does not exceed 16, as it will be clamped if it does. This instruction requires the VSX or Vector facility to be enabled in the MSR register, depending on the SX bit setting.

Example

plxvp vs1, 0(r4), 0

Encoding

Binary Layout
1
0
2
6
R
8
0
9
D0
14
58
32
XT
38
RA
43
D1
48
 
Format 8LS:D-form
Opcode 0x06000000
Extension Prefixed
Registers Altered MSR

Operands

  • XT
    Target
  • D
    Offset
  • RA
    Base
  • R
    PC-Rel