vavgsw

Vector Average Signed Word

vavgsw vD, vA, vB

Performs a vector average of signed words from two source vectors and stores the result in a destination vector.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1410

21:31

Format VA-form

Opcode 0x10000582

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vavgsw vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vavgsw, each word element in VSR[VRA+32] is added to the corresponding word element in VSR[VRB+32], incremented by 1, and then shifted right by 1 bit. The low-order 32 bits of the result are placed into the corresponding word element in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ← Chop32((src1 + src2 + 1) >> 1)

Programming Note

vavgsw is used for averaging signed word elements from two vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will be raised. The operation includes an implicit rounding by adding 1 before shifting right, which can affect results for negative numbers. This instruction operates on 32-bit word elements and requires proper alignment of input vectors.