xsmaddqp

VSX Scalar Multiply-Add Quad-Precision

xsmaddqp VRT,VRA,VRB

Performs a quad-precision floating-point multiply-add operation with rounding to even.

Details

This instruction multiplies two quad-precision floating-point numbers and adds the third number, rounding the result according to the specified mode.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRT+32])
src3 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_MULTIPLY_ADD(src1, src3, src2)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vximz_flag | vxisi_flag
ex_flag ← FPSCR.VE & vx_flag
if ex_flag=0 then do
    VSR[VRT+32] ← result
    FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

Programming Note

This instruction is used for performing a multiply-add operation on quad-precision floating-point numbers. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid exceptions. Be aware of rounding modes specified by FPSCR.RN and handle potential exceptions like VXSNAN, VXIMZ, Vxisi, OX, UX, and XX appropriately. The result is stored back into the destination register if no exceptions occur.

Example

xsmaddqp v1, v2, v3

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
RO
21
18
31
 
Format X-form
Opcode 0xFC000308
Extension VSX
Registers Altered FPSCR

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register