xvcvdpuxws

Vector Convert Double-Precision to Unsigned Word format with round to zero

xvcvdpuxws XT,XB

Converts double-precision floating-point values in a vector to unsigned 32-bit integers with rounding towards zero.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

800

21:31

Format XX2-form

Opcode 0xF0000320

Extension VSX

Operands

XT
Target Vector Register
XB
Source Vector Register

Example

xvcvdpuxws vs1, vs3

Registers Altered

FPSCR, VXSNAN, VXCVI, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction converts each element of the input vector from double-precision floating-point format to an unsigned 32-bit integer using round towards zero. If the rounded value is greater than 2^32 - 1, it results in 0xFFFF_FFFF and VXCVI is set to 1. If less than 0, it results in 0x0000_0000 and VXCVI is set to 1.

Operation

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
        if FPSCR.VXSNAN=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if Nmin-1 < src < Nmin then
        T(Nmin), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        T(f2i(trunc(src))), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        T(Nmax), fx(XX)
        if FPSCR.XX=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    else if src ≥ Nmax+1 then
        T(Nmax), fx(VXCVI)
        if FPSCR.VXCVI=0 and MSR.FE0!=ignore-exception-mode or MSR.FE1!=ignore-exception-mode then
            error()
        end if
    end if
end for

Programming Note

xvcvdpuxws rounds using Round towards Zero rounding mode. Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 and words 2 and 3 of the result register.