eieio
Enforce In-order Execution of I/O
eieio
Ensures that load/store instructions preceding the EIEIO complete before those following it. Used for Memory-Mapped I/O synchronization.
Encoding
Binary Layout
31
0:5
00000
6:10
00000
11:15
00000
16:20
854
21:30
/
31
Operands
Related
Across architectures
Memory Barrier / Fence : how x86, ARM, RISC-V, and PowerISA each do this.
More in Base
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
Enforces in-order completion of all load and store instructions issued before it with respect to all load and store instructions issued after it. This is essential for memory-mapped I/O synchronization and weak-ordering memory models. No condition register or status fields are affected.
Operation
Synchronize_IO()
Wait_for_all_preceding_loads_and_stores_to_complete()Programming Note
The eieio instruction is intended for use in doing memory-mapped I/O. Because loads, and separately stores, to storage that is both Caching Inhibited and Guarded are performed in program order (see Section 1.7.1, “Storage Access Ordering ” on page 973), eieio is needed for such storage only when loads must be ordered with respect to stores.