dadd.

Double Precision Add Record

dadd. FRD,FRB,FRC

Adds the contents of two double precision floating-point registers and updates the condition register.

Details

Adds two double-precision decimal floating-point operands and places the result in the target register, then updates CR1 based on the result, exception status, and FPSCR flags. This instruction requires the Decimal Floating-Point (DFP) category and updates FPSCR condition bits and CR1 field based on the result classification and exception conditions.

Pseudocode Operation

FRD ← FRB + FRC
CR1 ← FPSCR[FPRF]
FPSCR[exception bits] ← updated based on result

Programming Note

The dadd. instruction is used for adding two double-precision decimal floating-point numbers. It updates Condition Register Field 1 to indicate the result, which can be useful for conditional operations. Ensure that the input registers contain valid decimal floating-point values to avoid undefined behavior.

Example

dadd. f5, f3, f4

Encoding

Binary Layout
18
0
LI
6
AA
30
LK
31
 
Format XO-form
Opcode 0xEC000004
Extension Base
Registers Altered CR0, XER

Operands

  • FRD
    Target Double Precision Floating-Point Register
  • FRB
    Source Double Precision Floating-Point Register
  • FRC
    Source Double Precision Floating-Point Register