dadd.

Double Precision Add Record

dadd. FRD,FRB,FRC

Adds the contents of two double precision floating-point registers and updates the condition register.

Details

The dadd. instruction performs a decimal floating-point addition of the values in two floating-point registers (FRB and FRC) and stores the result in the target floating-point register FRD. The Rc=1 variant (dadd.) updates Condition Register Field 1 to reflect the result. This instruction operates on double-precision decimal floating-point values as defined in the IEEE 754-2008 decimal floating-point standard.

Pseudocode Operation

Not available in specification

Programming Note

The dadd. instruction is used for adding two double-precision decimal floating-point numbers. It updates Condition Register Field 1 to indicate the result, which can be useful for conditional operations. Ensure that the input registers contain valid decimal floating-point values to avoid undefined behavior.

Example

dadd. f5, f3, f4

Encoding

Binary Layout
18
0
LI
6
AA
30
LK
31
 
Format XO-form
Opcode 0xEC000005
Extension Base
Registers Altered CR0, XER

Operands

  • FRD
    Target Double Precision Floating-Point Register
  • FRB
    Source Double Precision Floating-Point Register
  • FRC
    Source Double Precision Floating-Point Register