pmxvbf16ger2np
Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate
Performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation.
Details
This instruction performs a masked vector operation with bfloat16 elements using negative multiplication and positive accumulation. It updates the accumulator register based on the specified masks and rounding mode.
Pseudocode Operation
if MSR.VSX=0 then VSX_Unavailable()
if 'xvbf16ger2' | 'xvbf16ger2pp' | 'xvbf16ger2pn' | 'xvbf16ger2np' | 'xvbf16ger2nn' then
do
PMSK ←0b11 // enable all rank updates
XMSK ←0b1111 // enable all ACC[AT] rows
YMSK ←0b1111 // enable all ACC[AT] columns
end
do i = 0 to 3
do j = 0 to 3
if XMSK.bit[i]=1 & YMSK.bit[j]=1 then do
src11 ←(PMSK.bit[0]=0) ? bfp_ZERO :
bfp_CONVERT_FROM_BFLOAT16(VSR[32×AX+A].word[i].hword[0])
src21 ←(PMSK.bit[0]=0) ? bfp_ZERO :
bfp_CONVERT_FROM_BFLOAT16(VSR[32×BX+B].word[j].hword[0])
src12 ←(PMSK.bit[1]=0) ? bfp_ZERO :
bfp_CONVERT_FROM_BFLOAT16(VSR[32×AX+A].word[i].hword[1])
src22 ←(PMSK.bit[1]=0) ? bfp_ZERO :
bfp_CONVERT_FROM_BFLOAT16(VSR[32×BX+B].word[j].hword[1])
reset_flags()
p1 ←bfp_MULTIPLY(src11, src21)
v1 ←bfp_MULTIPLY_ADD(src12, src22, p1)
r1 ←bfp_ROUND_TO_BFP32_SIGNIFICAND(v1)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if xx_flag=1 then SetFX(FPSCR.XX)
if 'pmxvbf16ger2' then do
reset_flags()
r2 ←bfp_ROUND_TO_BFP32_DEFAULT(FPSCR.RN,r1)
ACC[AT][i].word[j] ←bfp32_CONVERT_FROM_BFP(r2)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
end
else do
acc ←bfp_CONVERT_FROM_BFP32(ACC[AT][i].word[j])
reset_flags()
end
end
end
Programming Note
This instruction is used for performing a masked vector operation with bfloat16 elements, using negative multiplication and positive accumulation. It requires the VSX feature to be enabled in the MSR register. The instruction updates the accumulator register based on specified masks and rounding mode. Ensure that the VSX feature is available and properly configured before using this instruction.
Example
Encoding
Operands
-
AT
Target Accumulator Register -
XA
Source Vector Register A -
XB
Source Vector Register B -
XMSK
Row Mask for ACC[AT] -
YMSK
Column Mask for ACC[AT] -
PMSK
Prefix Mask