vaddcuq

Vector Add Carryout Unsigned Quadword

vaddcuq vD, vA, vB

Adds the contents of two vector registers and writes the carry-out to another register.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

1280

21:31

 

Format VX-form

Opcode 0x10000140

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B
• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

vaddcuq vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction adds the unsigned integer values in VSR[VRA+32] and VSR[VRB+32], placing the result in VSR[VRT+32]. The carry-out is also written into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
src1 ←EXTZ(VSR[VRA+32])
src2 ←EXTZ(VSR[VRB+32])
sum  ←EXTZ(src1) + EXTZ(src2)
VSR[VRT+32] ←EXTZ128((src1 + src2) >> 128)

Programming Note

The Vector Add Unsigned Quadword instructions support efficient wide-integer addition.