vclzdm

Vector Count Leading Zeros Doubleword under bit Mask

vclzdm VRT, VRA, VRB

Counts the number of leading zeros in each doubleword element of a vector, considering a mask.

Encoding

Binary Layout

0:5

6:29

Format X-form

Opcode 0x10000784

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vclzdm v1, v2, v3

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Counts the number of leading zero bits in each doubleword element of the source vector, using a bit mask from a second source vector to selectively apply the count operation. The results are placed in the target vector as doubleword elements. This is a VMX (AltiVec) category instruction that does not affect condition register or status fields.

Operation

for i in 0 to 1 do
  if VRB[i*64:(i+1)*64] != 0 then
    VRT[i*64:(i+1)*64] ← LEADING_ZEROS(VRA[i*64:(i+1)*64])
  else
    VRT[i*64:(i+1)*64] ← 0
end for

Programming Note

Use vclzdm to efficiently count leading zeros in masked bit positions within doublewords. Ensure that VRB contains a valid mask where 1s indicate bits to be considered for zero counting. This instruction operates at user privilege level and does not generate exceptions under normal conditions.