vcmpequq

Vector Compare Equal Quadword

vcmpequq VRT,VRA,VRB

Compares two quadwords and sets the result to all ones if they are equal, otherwise all zeros.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:31

Format VC-form

Opcode 0x100001C7

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vcmpequq v1, v2, v3

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares each quadword element of VRA with the corresponding quadword element of VRB for equality; the result for each quadword is all ones if equal or all zeros if not equal. If the Rc bit is set, CR6 is updated with summary information. Requires VMX support.

Operation

for i in 0 to 1 do
  if VRA[i*128:(i+1)*128-1] = VRB[i*128:(i+1)*128-1] then
    VRT[i*128:(i+1)*128-1] ← 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
  else
    VRT[i*128:(i+1)*128-1] ← 0x00000000000000000000000000000000
  end if
end for
if Rc then
  CR6 ← summary of results
end if

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.