vbpermd

Vector Bit Permute Doubleword

vbpermd VRT,VRA,VRB

Performs a bit permute operation on doublewords of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRA

11:15

VRB

16:31

 

Format VX-form

Opcode 0x100005CC

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Index Source Vector Register

Example

vbpermd v1, v2, v3

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bit permutation on doubleword elements of two vector registers. For each of the two doubleword elements in VRA, the bits are rearranged according to indices specified in the corresponding doubleword of VRB, with the result stored in VRT. No condition registers or status fields are affected.

Operation

for i in 0 to 1:
  for j in 0 to 63:
    bit_index ← VRB[i].doubleword[j][0:5]
    VRT[i].doubleword[j] ← VRA[i].doubleword[bit_index]

Programming Note

The vbpermd instruction is used to perform bit-level permutation on doublewords of two source vectors. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. Each byte in VRB acts as an index to select bits from VRA; if the index exceeds 63, the corresponding bit in the result is set to zero. This operation is useful for tasks requiring precise control over bit manipulation within vector registers.