vcmpgtuh

Vector Compare Greater Than Unsigned Halfword

vcmpgtuh vD, vA, vB

Unsigned > comparison for 8 halfwords.

Details

The vcmpgtuh instruction compares each unsigned halfword element of two vector registers and sets the corresponding result element to all 1s if the first element is greater than the second, otherwise to all 0s. It also updates the CR field if Rc=1.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
all_true ←1
all_false ←1
do i = 0 to 7
   src1 ←EXTZ(VSR[VRA+32].halfword[i])
   src2 ←EXTZ(VSR[VRB+32].halfword[i])
   if src1 > src2 then do
      VSR[VRT+32].halfword[i] ←0xFFFF
      all_false ←0
   end
   else do
      VSR[VRT+32].halfword[i] ←0x0000
      all_true ←0
   end
end
if Rc=1 then
   CR.field[6] ←all_true || 0b0 || all_false || 0b0

Programming Note

The vcmpgtuh instruction is commonly used for comparing unsigned halfword elements in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The instruction updates the CR field if Rc=1, which can be useful for conditional branching based on the comparison results.

Example

vcmpgtuh vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
582
21
 
Format VC-form
Opcode 0x10000246
Extension VMX (AltiVec)
Registers Altered MSR, CR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B