vcmpgtuh

Vector Compare Greater Than Unsigned Halfword

vcmpgtuh vD, vA, vB

Unsigned > comparison for 8 halfwords.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

582

21:31

 

Format VC-form

Opcode 0x10000246

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vcmpgtuh vd, va, vb

Registers Altered

MSR, CR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs an unsigned greater-than comparison of two vector registers on a halfword-by-halfword basis (8 halfwords) and stores a mask in the destination vector register, with all 1s where the comparison is true and all 0s where false. No CR or XER flags are modified by this instruction.

Operation

for i in 0 to 7 do
  if vA[i] > vB[i] (unsigned) then
    vD[i] ← 0xFFFF
  else
    vD[i] ← 0x0000

Programming Note

The vcmpgtuh instruction is commonly used for comparing unsigned halfword elements in vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The instruction updates the CR field if Rc=1, which can be useful for conditional branching based on the comparison results.