xscvqpudz
VSX Scalar Convert with round to zero Quad-Precision to Unsigned Doubleword format X-form
xscvqpudz VRT,VRB
Converts a quad-precision floating-point value to an unsigned doubleword integer, rounding towards zero.
Encoding
Binary Layout
63
0:5
VRT
6:10
17
11:15
VRB
16:20
836
21:30
/
31
Operands
-
VRT
Target Vector Register -
VRB
Source Vector Register
Example
xscvqpudz v1, v3
Registers Altered
FPSCR.FPRF, FPSCR.FR, FPSCR.FI, FPSCR.XX, FPSCR.VXSNAN, FPSCR.VXCVIRelated
More in VSX
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
The instruction converts the quad-precision floating-point value in VSR[VRB+32] to an unsigned doubleword integer, rounding towards zero. The result is placed into doubleword element 0 of VSR[VRT+32]. Doubleword element 1 of VSR[VRT+32] is set to 0.
Operation
if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ←bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
vxsnan_flag ←0
vxcvi_flag ←0
if src.class.QNaN=1 | src.class.SNaN=1 then do
result ←0x0000_0000_0000_0000
vxsnan_flag ←src.class.SNaN
vxcvi_flag ←1
end else if src.class.Infinity=1 then do
vxcvi_flag ←1
if src.sign=0 then
result ←0xFFFF_FFFF_FFFF_FFFF
else
result ←0x0000_0000_0000_0000
end
end else if src.class.Zero then
result ←0x0000_0000_0000_0000
else do
rnd ←bfp_ROUND_TO_INTEGER(0b001,src)
if bfp_COMPARE_GT(rnd, +264-1) then do
result ←0xFFFF_FFFF_FFFF_FFFF
vxcvi_flag ←1
end else if bfp_COMPARE_LT(rnd, 0) then do
result ←0x0000_0000_0000_0000
vxcvi_flag ←1
end else do
result ←ui64_CONVERT_FROM_BFP(rnd)
if xx_flag=1 then SetFX(FPSCR.XX)
end
end
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxcvi_flag=1 then SetFX(FPSCR.VXCVI)
vx_flag ←vxsnan_flag | vxcvi_flag
ex_flag ←FPSCR.VE & vx_flag
if ex_flag=0 then do
VSR[VRT+32].dword[0] ←result
VSR[VRT+32].dword[1] ←0x0000_0000_0000_0000
end
FPSCR.FR ←(vx_flag=0) & inc_flag
FPSCR.FI ←(vx_flag=0) & xx_flag
Programming Note
This instruction is used to convert a quad-precision floating-point number to an unsigned doubleword integer, rounding towards zero. Ensure the VSX facility is enabled; otherwise, it will raise an exception. Be cautious of NaNs and infinities, as they result in specific values and set condition flags. The operation does not require any particular alignment or privilege level.