divweu

Divide Word Extended Unsigned

divweu RT, RA, RB

Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.

Details

Performs unsigned extended division of a 64-bit dividend (RA || R0) by the 32-bit unsigned divisor in RB, placing the 32-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.

Pseudocode Operation

dividend ← (RA || 0)  # 64-bit value: RA in high 32 bits, 0 in low 32 bits
RT ← dividend / RB
if OE = 1 then
  XER[OV] ← overflow_flag
if Rc = 1 then
  CR0 ← (RT_comparison_summary)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divweu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
30
RB
OE
395
Rc
 
Format XO-form
Opcode 0x7C000316
Extension Base
Registers Altered CR0, XER

Operands

  • RT
    Target
  • RA
    Dividend
  • RB
    Divisor