divweu

Divide Word Extended Unsigned

divweu RT, RA, RB

Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

395

22:30

Rc

31

 

Format XO-form

Opcode 0x7C000316

Extension Base

Operands

• RT
  Target
• RA
  Dividend
• RB
  Divisor

Example

divweu r3, r4, r5

Registers Altered

CR0, XER

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs unsigned extended division of a 64-bit dividend (RA || R0) by the 32-bit unsigned divisor in RB, placing the 32-bit quotient in RT. If OE=1 and overflow occurs, the OV bit in XER is set; if Rc=1, CR0 is set based on the quotient. Division by zero produces undefined results.

Operation

dividend ← (RA || 0)  # 64-bit value: RA in high 32 bits, 0 in low 32 bits
RT ← dividend / RB
if OE = 1 then
  XER[OV] ← overflow_flag
if Rc = 1 then
  CR0 ← (RT_comparison_summary)

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.