divweu

Divide Word Extended Unsigned

divweu RT, RA, RB

Performs an unsigned division of a 64-bit dividend by a 32-bit divisor and returns the quotient in a 32-bit register.

Details

The divweu instruction divides the contents of two registers (RA and RB) treating them as a 64-bit unsigned integer, with RA being the high-order bits and RB being the low-order bits. The result is placed into RT.

Pseudocode Operation

if 'divweu' then
    RT <- (RA || RB) / RB

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divweu r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
30
RB
OE
395
Rc
 
Format XO-form
Opcode 0x7C000316
Extension Base
Registers Altered CR0, XER

Operands

  • RT
    Target
  • RA
    Dividend
  • RB
    Divisor