xsaddqp

VSX Scalar Add Quad-Precision

xsaddqp vD, vA, vB

Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).

Details

The xsaddqp instruction adds two quad-precision floating-point values, src1 and src2, and handles various special cases such as NaNs and exact-zero-difference results. The result is stored in the destination register VSR[VT+32].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP128(VSR[VRA+32])
src2 ← bfp_CONVERT_FROM_BFP128(VSR[VRB+32])
v ← bfp_ADD(src1, src2)
rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
result ← bfp128_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
  VSR[VRT+32] ← result
  FPSCR.FPRF ← fprf_CLASS_BFP128(result)
end
FPSCR.FR ← (vx_flag=0) & inc_flag
FPSCR.FI ← (vx_flag=0) & xx_flag

Programming Note

The xsaddqp instruction is used for adding two quad-precision floating-point numbers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of special cases like NaNs, which can set flags such as vxsnan_flag or vxisi_flag. The result is stored in VSR[VT+32], and proper rounding and exception handling are managed internally.

Example

xsaddqp v2, v3, v4

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
RO
21
11000000000000000000000000000000
31
 
Format X-form
Opcode 0xFC000004
Extension VSX
Registers Altered vxisi_flag, vxsnan_flag

Operands

  • vD
    Target (128-bit)
  • vA
    Source A
  • vB
    Source B
  • VRT
    Target Vector-Specific Register
  • VRA
    Source Vector-Specific Register
  • VRB
    Source Vector-Specific Register
  • VT
    Target Vector Register