xsaddqp

VSX Scalar Add Quad-Precision

xsaddqp vD, vA, vB

Adds two 128-bit Quad-Precision floating-point numbers held in VSX registers (pairs).

Encoding

Binary Layout

0

0:5

VRT

6:10

VRA

11:15

VRB

16:20

RO

21:30

11000000000000000000000000000000

31

 

Format X-form

Opcode 0xFC000008

Extension VSX

Operands

• vD
  Target (128-bit)
• vA
  Source A
• vB
  Source B
• VRT
  Target Vector-Specific Register
• VRA
  Source Vector-Specific Register
• VRB
  Source Vector-Specific Register
• VT
  Target Vector Register

Example

xsaddqp v2, v3, v4

// Scientific Quad-Float Add.

Registers Altered

vxisi_flag, vxsnan_flag

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds two 128-bit quad-precision floating-point numbers held in VSX register pairs and stores the result in another VSX register pair. The operation uses full precision during computation and rounds the result to quad-precision format. This instruction requires VSX support and updates FPSCR with exception flags as appropriate.

Operation

FPR[vD:vD+1] ← quad_precision(FPR[vA:vA+1] + FPR[vB:vB+1])
FPSCR ← updated with exception flags

Programming Note

The xsaddqp instruction is used for adding two quad-precision floating-point numbers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of special cases like NaNs, which can set flags such as vxsnan_flag or vxisi_flag. The result is stored in VSR[VT+32], and proper rounding and exception handling are managed internally.