vslh

Vector Shift Left Halfword

vslh vD, vA, vB

Shifts each halfword left.

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

324

21:31

 

Format VX-form

Opcode 0x10000144

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Data
• vB
  Shift

Example

vslh vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts each of the 8 halfword elements in vA left by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.

Operation

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← vA[i*16:i*16+15] << shift_amount

Programming Note

The vslh instruction shifts each halfword element of the source vector left by a specified number of bits. Ensure that the shift amount is within the valid range to avoid unexpected results. This instruction operates at the user privilege level and does not generate exceptions under normal conditions.