vsrh

Vector Shift Right Halfword

vsrh vD, vA, vB

Shifts the contents of each element in a vector right by a specified number of bits.

Encoding

Binary Layout

000100

0:5

6:10

11:15

16:20

01001

21:25

000100

26:31

Format VX-form

Opcode 0x10000244

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vsrh vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Shifts each of the 8 halfword elements in vA right (logically, without sign extension) by a variable number of bits specified by the low 4 bits of the corresponding halfword element in vB. Bits shifted out are lost; positions vacated are filled with zeros. No status flags are affected. This is a VMX/AltiVec instruction.

Operation

for i ← 0 to 7 do
  shift_amount ← vB[i*16:i*16+3]
  vD[i*16:i*16+15] ← vA[i*16:i*16+15] >> shift_amount

Programming Note

The vsrh instruction is used to perform element-wise right shifts on halfwords within a vector. Ensure that the shift amounts in the second source vector are within the range of 0-15 to avoid unexpected behavior. This instruction requires the VEC bit in the MSR register to be set; otherwise, it will raise an exception. Be cautious with alignment as unaligned access might lead to performance penalties or exceptions depending on the system configuration.