xsrdpic

VSX Scalar Round to Double-Precision Integer Exact using Current rounding mode

xsrdpic XT,XB

Rounds a double-precision floating-point value to an integer using the current rounding mode.

Details

The instruction rounds the double-precision floating-point value in doubleword element 0 of VSR[XB] to an integer using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, and doubleword element 1 of VSR[XT] is set to 0.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
src ←bfp_CONVERT_FROM_BFP64(VSR[VRB+32].dword[0])
if FPSCR.RN=0b00 then rnd ←bfp_ROUND_TO_INTEGER(0b000, src)
if FPSCR.RN=0b01 then rnd ←bfp_ROUND_TO_INTEGER(0b001, src)
if FPSCR.RN=0b10 then rnd ←bfp_ROUND_TO_INTEGER(0b010, src)
if FPSCR.RN=0b11 then rnd ←bfp_ROUND_TO_INTEGER(0b011, src)
result ←bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if xx_flag=1 then SetFX(FPSCR.XX)
vex_flag ←FPSCR.VE & vxsnan_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ←result
    VSR[32×TX+T].dword[1] ←0x0000_0000_0000_0000
    FPSCR.FPRF ←fprf_CLASS_BFP64(result)
    FPSCR.FR  ←inc_flag
    FPSCR.FI  ←xx_flag
else do
    FPSCR.FR  ←0b0
    FPSCR.FI  ←0b0
end

Programming Note

This instruction can be used to operate on a single-precision source operand. Previous versions of the architecture allowed the end contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.

Example

xsrdpic vs1, vs3

Encoding

Binary Layout
18
0
T
6
B
11
BX
16
TX
21
 
Format XX2-form
Opcode 0xF00001AC
Extension VSX
Registers Altered FPSCR, VXSNAN

Operands

  • XT
    Target Vector-Scalar Register
  • XB
    Source Vector-Scalar Register