mtvsrbm

Move to VSR Byte Mask

mtvsrbm VRT,RB

Moves a byte mask from a GPR to a VSR.

Encoding

Binary Layout

4

0:5

VRT

6:10

16

11:15

RB

16:20

17

21:31

 

Format VX-form

Opcode 0x10100642

Extension VMX (AltiVec)

Operands

• VRT
  Target Vector-Specific Register
• RB
  Source General Purpose Register

Example

mtvsrbm v1, r5

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of bits 48:63 of GPR[RB] are used to create a field mask in VSR[VRT+32]. Each bit in the GPR determines whether the corresponding byte in the VSR is set to all 0s or all 1s.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    if GPR[RB].bit[48+i]=0 then
        VSR[VRT+32].byte[i] ←0x00
    else
        VSR[VRT+32].byte[i] ←0xFF
end

Programming Note

This instruction is used to set each byte in a vector register to either all zeros or all ones based on the bits in a general-purpose register. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The instruction processes 16 bytes, so ensure that the GPR contains valid bit values for positions 48 to 63.