bcdsr.
Binary Coded Decimal Shift and Round
Shifts a binary coded decimal value by a specified number of digits and rounds the result.
Details
The bcdsr. instruction shifts a signed packed decimal value in VSR[VRB+32] by a number of digits specified by the signed integer value in byte element 7 of VSR[VRA+32]. The result is rounded and placed into VSR[VRT+32].
Pseudocode Operation
if MSR.VEC=0 then
Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
end
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ←(VSR[VRB+32].nibble[0:30] = 0)
gt_flag ←(eq_flag=0) & (src_sign=0)
lt_flag ←(eq_flag=0) & (src_sign=1)
n ←EXTS(VSR[VRA+32].byte[7])
if n > 0 then do // shift left
shcnt ←Clamp(n, 0, 31)
src.nibble[0:30] ←VSR[VRB+32].nibble[0:30]
src.nibble[31:61] ←0
result.nibble[0:30] ←src.nibble[shcnt:shcnt+30]
ox_flag ←(shcnt > 0) & (src.nibble[0:shcnt-1] != 0)
g_flag ←0
end else do // shift right
shcnt ←Clamp(¬n + 1, 0, 31)
src.nibble[31:61] ←VSR[VRB+32].nibble[0:30]
ox_flag ←0
g_flag ←(shcnt > 0) & (EXTZ(src.nibble[62-shcnt]) >= 5)
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
result ←(g_flag=0) ? result : bcd_INCREMENT(result)
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flagProgramming Note
The bcdsr. instruction is used for shifting and rounding packed decimal values in vector registers. Ensure the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector_Unavailable exception will occur. The instruction handles both left and right shifts based on the sign of the shift count in byte element 7 of the source register. Be cautious with invalid input detection, as any nibble outside the range 0x0 to 0x9 or special nibbles (0xB, 0xD) will set the CR6[3] bit and result in undefined output.
Example
Encoding
Operands
-
VRT
Target Vector Register -
VRA
Source Vector Register containing the shift count -
VRB
Source Vector Register containing the packed decimal value to be shifted and rounded -
PS
Packed Sign field