lq

Load Quadword

lq RTp, DQ(RA)

Loads 128 bits into two adjacent GPRs (Even/Odd pair).

Encoding

Binary Layout

0:5

RTp

6:10

11:15

16:27

28:31

Format DQ-form

Opcode 0xE0000000

Extension Base

Operands

RTp
Target Pair
DQ
Disp
RA
Base
disp
Displacement value
EA
Effective Address

Example

lq r4, 0(r4)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For lq, the quadword in storage addressed by EA is loaded into an even-odd pair of GPRs. In Big-Endian mode, the even-numbered GPR is loaded with the doubleword from storage addressed by EA and the odd-numbered GPR is loaded with the doubleword addressed by EA+8. In Little-Endian mode, the even-numbered GPR is loaded with the byte-reversed doubleword from storage addressed by EA+8 and the odd-numbered GPR is loaded with the byte-reversed doubleword addressed by EA.

Operation

if 'lq' then
    EA ← (RA|0) + EXTS64(DQ||0b0000)
    if Big-Endian byte ordering then
        RTp||RTp+1 ← MEM(EA,16)
    if Little-Endian byte ordering then
        RTp||RTp+1 ← MEM(EA,16)

Programming Note

The lq and stq instructions exist primarily to permit software to access quadwords in storage “atomically”.

lq