stbcix

Store Byte Caching Inhibited Indexed X-form

stbcix RS,RA,RB

Stores a byte from a register to memory with caching inhibited and guarded.

Encoding

Binary Layout

0

0:5

RS

6:10

RA

11:15

RB

16:31

 

Format X-form

Opcode 0x7C0007AA

Extension Base

Operands

• RS
  Source General Purpose Register
• RA
  Base Address General Purpose Register
• RB
  Index General Purpose Register

Example

stbcix r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction stores the byte (RS)56:63 into the memory location addressed by the effective address (EA), which is calculated as the sum of RA and RB. The storage access is performed as though the specified storage location is Caching Inhibited and Guarded.

Operation

if RA = 0 then
    b ← 0
else
    b ← (RA)
EA ← b + (RB)
MEM(EA, 1) ← (RS)56:63

Programming Note

This instruction is hypervisor privileged.