xvcmpgedp

VSX Vector Compare Greater or Equal Double-Precision

xvcmpgedp XT,XA,XB
xvcmpgedp. XT,XA,XB

Compares two double-precision floating-point values and sets the target vector register based on the comparison.

Details

For xvcmpgedp, each integer value i from 0 to 1, the double-precision floating-point operand in doubleword element i of VSR[XA] is compared to the double-precision floating-point operand in doubleword element i of VSR[XB]. The contents of doubleword element i of VSR[XT] are set to all 1s if src1 is greater than or equal to src2, and is set to all 0s otherwise.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
ex_flag ←0b0
all_false ←0b1
all_true ←0b1
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    if src1.class.SNaN | src2.class.SNaN then do
        vxsnan_flag ←0b1
        if FPSCR.VE=0 then vxvc_flag ←0b1
    end
    else vxvc_flag ←IsQNaN(src1) | IsQNaN(src2)
    if src1 >= src2 then do
        vresult.dword[i] ←0xFFFF_FFFF_FFFF_FFFF
        all_false ←0b0
    end
    else do
        vresult.dword[i] ←0x0000_0000_0000_0000
        all_true ←0b0
    end
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxvc_flag=1 then SetFX(FPSCR.VXVC)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxvc_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←vresult
if Rc=1 then do
    if vex_flag=0 then CR.field[6] ←all_true || 0b0 || all_false || 0b0
    else CR.field[6] ←0bUUUU
end

Programming Note

When Rc=1, CR1 is set from the FPSCR[FX, FEX, VX, OX] bits immediately after the operation completes.

Example

xvcmpgedp vs1, vs2, vs3

Encoding

Binary Layout
T
0
A
6
B
11
Rc
16
115
21
AX
22
BX
29
TX
30
 
Format XX3-form
Opcode 0xF0000073
Extension VSX
Registers Altered CR6, FPSCR

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register