vpmsumb

Vector Polynomial Multiply-Sum Byte

vpmsumb vD, vA, vB

Performs GF(2) polynomial arithmetic (Carryless Multiply) on bytes.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1032

21:31

Format VX-form

Opcode 0x10000408

Extension Vector Crypto

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vpmsumb vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vpmsumb, each byte element in VSR[VRA+32] is multiplied by each byte element in VSR[VRB+32], and the results are summed. The final result is stored in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    prod[i].bit[0:14] ←0
    srcA ←VSR[VRA+32].byte[i]
    srcB ←VSR[VRB+32].byte[i]
    do j = 0 to 7
        do k = 0 to j
            gbit ←srcA.bit[k] & srcB.bit[j-k]
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
    do j = 8 to 14
        do k = j-7 to 7
            gbit ←(srcA.bit[k] & srcB.bit[j-k])
            prod[i].bit[j] ←prod[i].bit[j] ⊕gbit
        end
    end
end
do i = 0 to 7
    VSR[VRT+32].hword[i] ←0b0 || (prod[2×i] ⊕prod[2×i+1])
end

Programming Note

The vpmsumb instruction performs a polynomial multiplication and summation on byte elements of vector registers. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 16-byte vectors, so input and output vectors must be properly aligned. Be cautious with handling overflow as the result is truncated to fit into the destination register.