andi.

AND Immediate D-form with Record Update

andi. RA, RS, UI

Performs a bitwise AND operation between the contents of a register and an immediate value, and updates the condition register.

Encoding

Binary Layout

28

0:5

RS

6:10

RA

11:15

UI

16:31

 

Format D-form

Opcode 0x70000000

Extension Base

Operands

• RA
  Target Register
• RS
  Source Register
• UI
  Unsigned 16-bit Immediate
• RT
  Target General Purpose Register

Example

andi. r3, r4, 0xF

// r3 = r4 & 0xF

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of register RS are ANDed with 480 || UI and the result is placed into register RA. The first three bits of CR Field 0 are set as described in Section 3.3.8.

Operation

RA <- (RS) & (0x0000 || UI); CR0 <- Compare(RA, 0)

Programming Note

The andi. instruction performs a bitwise AND operation between the contents of register RS and an immediate value UI, storing the result in RA. It also updates CR0 to reflect if the result is zero or not. Ensure that the immediate value fits within 16 bits as it is zero-extended to 32 bits before the operation.