addg6s

Add and Generate Sixes

addg6s RT,RA,RB

Adds the contents of two registers and generates sixes based on carry bits.

Encoding

Binary Layout

18

0:5

LI

6:29

AA

30

LK

31

 

Format XO-form

Opcode 0x7C000094

Extension Base

Operands

• RT
  Target General Purpose Register
• RA
  Source General Purpose Register
• RB
  Source General Purpose Register

Example

addg6s r3, r4, r5

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds the values in registers RA and RB, then replaces each nibble (4-bit group) of the result with 0x6 if a carry was generated from that nibble, otherwise the low 4 bits of the sum are preserved. This instruction is used in decimal arithmetic for BCD (Binary Coded Decimal) addition to generate correction factors. No condition or status registers are affected, and the Rc bit is not available (non-dot form only).

Operation

sum ← (RA) + (RB); for i = 0 to 15: if carry_from_nibble(i) then RT[4i:4i+3] ← 0x6 else RT[4i:4i+3] ← sum[4i:4i+3]

Programming Note

addg6s can be used to add or subtract two BCD operands. In these examples it is assumed that r0 contains 0x666...666. (BCD data formats are described in Section 5.3.)