xvcvdpsp

Vector Convert Double-Precision to Single-Precision

xvcvdpsp XT, XB

Converts double-precision floating-point values in a vector to single-precision format.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

393

21:31

Format XX2-form

Opcode 0xF0000624

Extension VSX

Operands

XT
Target
XB
Source

Example

xvcvdpsp vs1, vs3

Registers Altered

FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts two double-precision floating-point values in VSR[XB] to single-precision format and places the results in VSR[XT]. The two double-precision elements (0 and 1) are converted and packed into the single-precision elements (0 and 1) of the target. Rounding is performed according to the current rounding mode in FPSCR.

Operation

VSR[XT].element[0] ← ConvertDP_to_SP(VSR[XB].element[0])
VSR[XT].element[1] ← ConvertDP_to_SP(VSR[XB].element[1])

Programming Note

Previous versions of the architecture allowed the contents of bits 32:63 of each doubleword in the result register to be undefined, however, all processors that support this instruction write the result into bits 32:63 of each doubleword in the result register as well as into bits 0:31, as is required by this version of the architecture. Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.