xvcvdpsp

Vector Convert Double-Precision to Single-Precision

xvcvdpsp XT, XB

Converts double-precision floating-point values in a vector to single-precision format.

Details

The xvcvdpsp instruction converts each double-precision floating-point value in the source vector VSR[XB] to single-precision format and stores the result in the target vector VSR[XT]. The rounding mode is specified by the FPSCR.RN field. If a Signalling NaN is encountered, it is converted to a Quiet NaN, and VXSNAN is set.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,src)
    vresult.dword[i].word[0] ← bfp32_CONVERT_FROM_BFP(rnd)
    vresult.dword[i].word[1] ← 0
    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)
    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end
if ex_flag=0 then VSR[32×TX+T] ←result

Programming Note

['Previous versions of the architecture allowed the contents of bits 32:63 of each doubleword in the result register to be undefined, however, all processors that support this instruction write the result into bits 32:63 of each doubleword in the result register as well as into bits 0:31, as is required by this version of the architecture.', 'Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.']

Example

xvcvdpsp vs1, vs3

Encoding

Binary Layout
60
16
XT
11
0
6
XB
0
393
 
Format XX2-form
Opcode 0xF0000189
Extension VSX
Registers Altered FPSCR

Operands

  • XT
    Target
  • XB
    Source