vmsumshm

Vector Multiply-Sum Signed Halfword Modulo

vmsumshm vD, vA, vB, vC

Multiplies halfwords and sums adjacent results into words.

Details

The Vector Multiply-Sum Signed Halfword Modulo instruction performs a multiply-sum operation on signed halfwords from two input vectors and adds the result to an accumulator vector. The results are modulo 32,768.

Pseudocode Operation

for i = 0 to 15:
    result[i] ← (a[i] * b[i]) + c[i]
    if result[i] >= 32768:
        result[i] ← result[i] - 32768
    else if result[i] < -32768:
        result[i] ← result[i] + 32768

Programming Note

This instruction is useful for performing vectorized multiply-sum operations on signed halfwords, ensuring results are within the range of a 16-bit signed integer by applying modulo arithmetic. Ensure that input vectors and accumulator are properly aligned to avoid performance penalties. This operation does not require any special privileges but can generate exceptions if input data exceeds expected ranges.

Example

vmsumshm vd, va, vb, vc

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
VRC
21
40
26
 
Format VA-form
Opcode 0x10000028
Extension VMX (AltiVec)
Registers Altered VSCR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • vC
    Accumulator
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • VRC
    Source Vector Register