vmsumshm

Vector Multiply-Sum Signed Halfword Modulo

vmsumshm vD, vA, vB, vC

Multiplies halfwords and sums adjacent results into words.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

VRC

21:25

26:31

Format VA-form

Opcode 0x10000028

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
vC
Accumulator
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VRC
Source Vector Register

Example

vmsumshm vd, va, vb, vc

Registers Altered

VSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies four pairs of signed halfword elements from vA and vB, then sums the adjacent pairs of products modulo 2^32 and adds the corresponding word element from vC (accumulator), storing the result in vD. This instruction operates on Classic VMX (AltiVec) and does not set any condition flags.

Operation

for i in 0 to 1 do
  prod_hi ← vA[i*2] × vB[i*2]
  prod_lo ← vA[i*2+1] × vB[i*2+1]
  vD[i] ← (prod_hi + prod_lo + vC[i]) mod 2^32
endfor

Programming Note

This instruction is useful for performing vectorized multiply-sum operations on signed halfwords, ensuring results are within the range of a 16-bit signed integer by applying modulo arithmetic. Ensure that input vectors and accumulator are properly aligned to avoid performance penalties. This operation does not require any special privileges but can generate exceptions if input data exceeds expected ranges.