xscvdpsxws

VSX Scalar Convert Double-Precision to Signed Word format with round to zero

xscvdpsxws XT,XB

Converts a double-precision floating-point value to a signed word format using round towards zero.

Encoding

Binary Layout
60
0:5
XT
6:10
/
11:15
XB
16:20
352
21:31
 
Format X-form
Opcode 0xF0000160
Extension VSX

Operands

  • XT
    Target Vector-Scalar Register
  • XB
    Source Vector-Scalar Register
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register

Example

xscvdpsxws vs1, vs3

Registers Altered

FPSCR, VXSNAN, VXCVI, XX

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts a double-precision floating-point value from the source VSR to a signed 32-bit word integer using round-toward-zero mode and stores the result in the target VSR. Only the scalar (leftmost) element is processed. Invalid conversions produce a saturated value; the FPSCR is updated with status flags.

Operation

XT[0:31] ← ConvertToSignedWord_RoundTowardZero(XB[0:63])
XT[32:127] ← 0

Programming Note

Previous versions of the architecture allowed the contents of word 0 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 of the result register, as is required by this version of the architecture. This instruction can be used to operate on a single-precision source operand. xscvdpsxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode, including xsrdpic which uses the rounding mode specified by RN.