xscvdpsxws
VSX Scalar Convert Double-Precision to Signed Word format with round to zero
Converts a double-precision floating-point value to a signed word format using round towards zero.
Details
The xscvdpsxws instruction converts the double-precision floating-point value in VSR[XB].dword[0] to a signed 32-bit integer and places it into VSR[XT].word[0] and VSR[XT].word[1]. If the result is out of range, it saturates to the minimum or maximum signed 32-bit integer value.
Pseudocode Operation
if src ≤ Nmin - 1 then
T(Nmin)
fr(0)
fi(0)
fx(VXCVI)
else if Nmin - 1 < src < Nmin then
T(Nmin)
fr(0)
fi(1)
fx(XX)
error()
else if src = Nmin then
T(Nmin)
fr(0)
fi(0)
else if Nmin < src < Nmax then
T(f2i(trunc(src)))
fr(0)
fi(1)
fx(XX)
error()
else if src = Nmax then
T(Nmax)
fr(0)
fi(0)
else if Nmax < src < Nmax + 1 then
T(Nmax)
fr(0)
fi(1)
fx(XX)
error()
else if src ≥ Nmax + 1 then
T(Nmin)
fr(0)
fi(0)
fx(VXCVI)
else if src is a QNaN then
T(Nmin)
fr(0)
fi(0)
fx(VXCVI)
else if src is a SNaN then
T(Nmin)
fr(0)
fi(0)
fx(VXCVI)
fx(VXSNAN)Programming Note
['Previous versions of the architecture allowed the contents of word 0 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 of the result register, as is required by this version of the architecture.', 'This instruction can be used to operate on a single-precision source operand.', 'xscvdpsxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Double-Precision Integer instruction that corresponds to the desired rounding mode, including xsrdpic which uses the rounding mode specified by RN.']
Example
Encoding
Operands
-
XT
Target Vector-Scalar Register -
XB
Source Vector-Scalar Register -
VRT
Target Vector Register -
VRA
Source Vector Register