vslw

Vector Shift Left Word

vslw vD, vA, vB

Shifts each of the four words in vA left by the number of bits specified in the corresponding word of vB.

Details

For vslw, each word element of VSR[VRA+32] is shifted left by the number of bits specified in the low-order 5 bits of the corresponding word element of VSR[VRB+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i].bit[27:31]
    VSR[VRT+32].word[i] ← src1 << src2

Programming Note

The vslw instruction shifts each word element of the source vector left by a specified number of bits. Ensure that the shift amount is within the range 0-31 to avoid undefined behavior. This operation requires the Vector Facility to be enabled in the MSR register; otherwise, it will raise an exception.

Example

vslw v1, v2, v3

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
388
 
Format VX-form
Opcode 0x10000184
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Source Data
  • vB
    Shift Amounts
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register