dsub

Decimal Subtract

dsub FRT,FRA,FRB

Subtracts the contents of two DFP registers and places the result in another DFP register.

Encoding

Binary Layout

0:5

FRT

6:10

FRA

11:15

FRB

16:20

514

21:30

Format X-form

Opcode 0xEC000404

Extension Decimal Floating-Point

Operands

FRT
Target
FRA
Src A
FRB
Src B

Example

dsub f1, f2, f3

Registers Altered

FPSCR, FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, CR1

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The DFP operand in FRB[p] is subtracted from the DFP operand in FRA[p]. The result is rounded to the target-format precision under control of DRN (bits 29:31 of the FPSCR). An appropriate form of the rounded result is selected based on the ideal exponent and is placed in FRT[p]. The ideal exponent is the smaller exponent of the two source operands.

Operation

if 'dsub' then
    FRT[p] <- (FRA[p]) - (FRB[p])

Programming Note

The dsub instruction performs a decimal subtraction between two DFP operands. Ensure that both operands are properly aligned and formatted according to the target precision specified in the FPSCR register. Be aware of potential rounding errors based on the current rounding mode set in DRN, and check for any exceptions or flags (like VXSNAN) that may indicate invalid operations or special results.