fcmpu

Floating Compare Unordered

fcmpu BF, FRA, FRB

Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.

Details

The fcmpu instruction compares the contents of two floating-point registers, FRA and FRB. It sets one bit in the designated CR field to 1 and the other three to 0, and updates the FPCC accordingly. The comparison is unordered, meaning it does not consider the sign of zero.

Pseudocode Operation

if (FRA) is a NaN or
     (FRB) is a NaN then c ←0b0001
else if (FRA) < (FRB) then c ←0b1000
else if (FRA) > (FRB) then c ←0b0100
else                       c ←0b0010
FPCC ←c
CR4×BF:4×BF+3 ←c
if (FRA) is an SNaN or
     (FRB) is an SNaN then
  VXSNAN ←1
  if VE = 0 then VXVC ←1

Programming Note

The fcmpu instruction is commonly used for unordered floating-point comparisons, which are useful in scenarios where NaN values need to be handled gracefully. Be cautious with signaling NaNs (SNaNs), as they can trigger exceptions and set the VXSNAN flag. Ensure that the FPSCR and CR registers are properly managed to handle comparison results and exceptions correctly.

Example

fcmpu cr0, f1, f2

Encoding

Binary Layout
63
0
BF
6
/
9
FRA
11
FRB
16
0000000000
21
/
31
 
Format X-form
Opcode 0xFC000000
Extension Floating-Point
Registers Altered FPSCR, CR

Operands

  • BF
    CR Field
  • FRA
    Source A
  • FRB
    Source B
  • CRb
    Condition Register Field
  • FRa
    Floating-Point Register Source
  • FRc
    Floating-Point Register Source