fcmpu

Floating Compare Unordered

fcmpu BF, FRA, FRB

Compares two floating-point registers and sets the Condition Register (CR) field. Does not trap on NaNs.

Encoding

Binary Layout

0:5

6:8

9:10

FRA

11:15

FRB

16:20

0000000000

21:30

Format X-form

Opcode 0xFC000000

Extension Floating-Point

Operands

BF
CR Field
FRA
Source A
FRB
Source B
CRb
Condition Register Field
FRa
Floating-Point Register Source
FRc
Floating-Point Register Source

Example

fcmpu cr0, f1, f2

// Compare f1 vs f2.

Registers Altered

FPSCR, CR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares two floating-point registers (FRA and FRB) and writes the result (less-than, equal, greater-than, or unordered) into the specified CR field (BF). Unlike fcmpo, this instruction does not trap on signaling NaN operands. The FPSCR may record VXCC (invalid operation) for signaling NaNs.

Operation

if (FRA) is NaN or (FRB) is NaN then
  CR[BF] ← 0b0001
  FPSCR[VXCC] ← 1
elif (FRA) < (FRB) then
  CR[BF] ← 0b1000
elif (FRA) > (FRB) then
  CR[BF] ← 0b0100
else
  CR[BF] ← 0b0010

Programming Note

The fcmpu instruction is commonly used for unordered floating-point comparisons, which are useful in scenarios where NaN values need to be handled gracefully. Be cautious with signaling NaNs (SNaNs), as they can trigger exceptions and set the VXSNAN flag. Ensure that the FPSCR and CR registers are properly managed to handle comparison results and exceptions correctly.