vextsw2d

Vector Extend Sign Word To Doubleword

vextsw2d vD, vB

Extends the sign of each word in a vector to doubleword.

Details

The signed integer in bits 32:63 of each doubleword element of VSR[VRB+32] is sign-extended and placed into the corresponding doubleword element of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRB+32].dword[i].bit[32:63]
    VSR[VRT+32].dword[i] ← EXTS64(src)
end

Programming Note

This instruction is used to sign-extend the upper 32 bits of each doubleword in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes two elements per iteration, and it's important to verify that the source and target registers are correctly aligned for optimal performance.

Example

vextsw2d vd, vb

Encoding

Binary Layout
4
0
vD
6
0
11
vB
16
1926
 
Format VX-form
Opcode 0x10000786
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vB
    Source
  • VRT
    Target Vector Register
  • VRB
    Source Vector Register