vextsw2d

Vector Extend Sign Word To Doubleword

vextsw2d vD, vB

Extends the sign of each word in a vector to doubleword.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1926

21:31

 

Format VX-form

Opcode 0x101A0602

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vextsw2d vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The signed integer in bits 32:63 of each doubleword element of VSR[VRB+32] is sign-extended and placed into the corresponding doubleword element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 1
    src ← VSR[VRB+32].dword[i].bit[32:63]
    VSR[VRT+32].dword[i] ← EXTS64(src)
end

Programming Note

This instruction is used to sign-extend the upper 32 bits of each doubleword in a vector register. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes two elements per iteration, and it's important to verify that the source and target registers are correctly aligned for optimal performance.