lhzu

Load Halfword and Zero with Update D-form

lhzu RT,D(RA)

Loads a halfword from memory into a register, zero-extends it to 64 bits, and updates the base address.

Encoding

Binary Layout

0

0:5

RT

6:10

RA

11:15

D

16:31

 

Format D-form

Opcode 0xA4000000

Extension Base

Operands

• RT
  Target General Purpose Register
• RA
  Base General Purpose Register
• D
  Displacement

Example

lhzu r3, 0(r4)

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The effective address (EA) is calculated as the sum of the contents of register RA and the sign-extended displacement D. The halfword at EA is loaded into RT48:63, with RT0:47 set to zero. The EA is then placed back into RA.

Operation

EA ← (RA) + EXTS(D)
RT ← 480 || MEM(EA, 2)
RA ← EA

Programming Note

The base register (RA) is updated with the effective address after the memory access. RA must not be 0 and must differ from the destination register; violating this constraint produces undefined results.