lwarx

Load Word and Reserve Indexed

lwarx EH=0 RT,RA,D

Loads a word and creates a reservation for use with 'stwcx.'. Critical for implementing atomic primitives (mutexes).

Encoding

Binary Layout
31
0:5
RT
6:10
RA
11:15
RB
16:20
20
21:30
EH
31
 
Format X-form
Opcode 0x7C000028
Extension Base

Operands

  • RT
    Target Register
  • RA
    Base Register
  • RB
    Index Register
  • D
    Immediate Displacement
  • EH
    Hint for subsequent store operation

Example

lwarx r3, 0, r4

// Start atomic read-modify-write.

Registers Altered

XER, LR

Related

Across architectures

Atomic Compare and Swap : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 32-bit word from memory at address (RA + RB) and places it into RT, and creates a reservation on that cache line for atomic updates with stwcx. The optional EH field (bit 31) provides a hint about the expected success of a subsequent conditional store. This instruction is critical for implementing atomic operations and locks. No condition or status registers are modified by this instruction itself.

Operation

EA ← (RA) + (RB)
RT ← sign_extend([EA+3:EA])
RESERVATION_VALID ← 1
RESERVATION_ADDR ← page_address(EA)
// EH field (bit 31) is a hint for subsequent stwcx.

Extended Mnemonics

Extended Mnemonic Equivalent Instruction
lwarx

Programming Note

EH = 0 should be used when all accesses to a mutex variable are performed using an instruction sequence with Load And Reserve followed by Store Conditional. EH = 1 should be used when the program is obtaining a lock variable which it will subsequently release before another program attempts to perform a store to it.