stmw

Store Multiple Word

stmw RT, D(RA)

Stores words from registers RT through R31 to memory (Context Switch).

Details

Stores a sequence of words from GPRs RT through R31 to memory starting at address (RA + D), incrementing the address by 4 bytes for each register. This instruction is part of the Base ISA and does not update condition registers; it is commonly used for context switching.

Pseudocode Operation

if RA = 0 then EA ← 0 + D else EA ← RA + D
for i ← 0 to (31 - RT) do
  MEM[EA+4*i : EA+4*i+31] ← GPRC[RT+i]
end for

Programming Note

Loads (or stores) a sequence of GPRs from consecutive word-aligned memory locations. Not pipelined on most implementations; for bulk data movement consider using vector or floating-point load/store multiples instead.

Example

stmw r3, 0(r4)

Encoding

Binary Layout
47
0
RT
6
RA
11
D
16
 
Format D-form
Opcode 0xBC000000
Extension Base

Operands

  • RT
    Start Register
  • D
    Displacement
  • RA
    Base