xxlxor

VSX Vector Logical XOR

xxlxor XT, XA, XB

Bitwise XOR.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

456

21:31

 

Format XX3-form

Opcode 0xF00004D0

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xxlxor vs1, vs2, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a bitwise logical XOR of the contents of XA and XB, storing the result in XT. This is a VSX instruction that does not affect condition or status flags.

Operation

XT ← XA XOR XB

Programming Note

The xxlxor instruction requires the VSX facility to be enabled; otherwise, it will raise an exception. Ensure that the VSX bit in the MSR register is set before using this instruction. The operation is performed on 128-bit vector registers, so ensure proper alignment and that the input registers contain valid data for accurate results.