xxpermr

VSX Vector Permute Right

xxpermr XT, XA, XB, XC

Little-endian optimized permute.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:25

26:31

Format XX4-form

Opcode 0xF00001D0

Extension VSX

Operands

XT
Target
XA
Src A
XB
Src B
XC
Control

Example

xxpermr vs1, vs2, vs3, vs4

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Permutes bytes from two 128-bit VSX registers (XA and XB) using a control vector in XC, optimized for little-endian byte ordering. Each byte in the control vector specifies which byte from the concatenation of XB and XA is selected into the corresponding output byte in XT. This is a VSX category instruction with no effect on condition registers.

Operation

concat ← XB || XA
for i ← 0 to 15
  control_byte ← XC[8*i:8*i+7]
  idx ← control_byte[1:4]
  XT[8*i:8*i+7] ← concat[8*idx:8*idx+7]

Programming Note

The xxpermr instruction is useful for complex byte-level data manipulation, especially when merging and reordering bytes from two source vectors. Ensure that the control vector (second source) correctly specifies the desired permutation indices to avoid unexpected results. This instruction operates at a privilege level that allows it in user mode, but developers should be cautious of potential performance overhead due to its complexity.