lxvh8x

Load VSX Vector Halfword*8 Indexed

lxvh8x XT,RA,RB

Loads a vector of 8 halfwords from memory into a VSX register.

Encoding

Binary Layout

0

0:5

T

6:10

RA

11:15

RB

16:20

TX

21:31

 

Format X-form

Opcode 0x7C000658

Extension VSX

Operands

• XT
  Target VSX Register
• RA
  Source General Purpose Register (Base Address)
• RB
  Source General Purpose Register (Index)

Example

lxvh8x vs1, r4, r5

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 128-bit vector containing 8 halfword elements from memory into a VSX register. The effective address is computed as RA|0 + RB. No status fields are modified by this instruction.

Operation

EA ← (RA=0 ? 0 : GPR[RA]) + GPR[RB]
VSR[XT] ← MEM(EA, 16)

Programming Note

lxvh8x, lxvd2x, lxvw4x, lxvb16x, and lxvx exhibit identical behavior in Big-Endian mode.