addis

Add Immediate Shifted

addis RT, RA, SI

Adds an immediate value shifted left by 16 bits to the contents of a register and places the result in another register.

Encoding

Binary Layout

001111

0:5

6:10

11:15

SIMM

16:31

Format D-form

Opcode 0x3C000000

Extension Base

Operands

RT
Target Register
RA
Source Register (0 means 0)
SI
Signed 16-bit Immediate
SIMM
16-bit signed immediate value shifted left by 16 bits

Example

addis r3, r4, 1

// r3 = r4 + 65536 (0x10000)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds the signed 16-bit immediate SI shifted left by 16 bits to register RA (or 0 if RA=0) and stores the result in RT. This is commonly used to load the high-order 16 bits of a 32-bit constant. No condition registers or XER flags are affected.

Operation

RT ← (RA | 0) + (sign_extend(SI) << 16)

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction
lis
subis

Programming Note

The addis instruction is commonly used for loading large immediate values into a register by shifting the 16-bit immediate value left by 16 bits and adding it to the contents of another register. If RA is zero, the instruction effectively sign-extends the immediate value and places it in RT. This instruction does not require any special privileges and can be used at any privilege level. However, developers should ensure that the immediate value does not cause overflow when shifted and added, as this could lead to unexpected results.