divwe

Divide Word Extended

divwe RT, RA, RB

Performs a signed division of a 64-bit dividend by a 32-bit divisor and places the result in a 32-bit register.

Details

The 64-bit dividend is formed from the upper 32 bits of RA (RA32:63) concatenated with 320. The 32-bit divisor is taken from RB (RB32:63). If the quotient can be represented in 32 bits, it is placed into RT32:63. The contents of RT0:31 are undefined.

Pseudocode Operation

if 'divwe' then
    dividend0:63 ← (RA)32:63 || 320
    divisor0:31 ← (RB)32:63
    RT32:63 ← dividend ÷ divisor
    RT0:31 ← undefined

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divwe r3, r4, r5

Encoding

Binary Layout
0
0
RT
6
RA
11
RB
16
OE
21
427
22
Rc
31
31
 
Format XO-form
Opcode 0x7C000356
Extension Base
Registers Altered CR0, XER

Operands

  • RT
    Target
  • RA
    Dividend
  • RB
    Divisor