dmul

Decimal Multiply

dmul FRT,FRA,FRB
dmul. FRT,FRA,FRB

Multiplies the contents of two DFP registers and places the result in another DFP register.

Details

Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.

Pseudocode Operation

FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Programming Note

dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.

Example

dmul f1, f2, f3

// Financial Multiply.

Encoding

Binary Layout
0
0
FRT
6
FRA
11
FRB
16
Rc
21
0
26
0
27
0
31
 
Format X-form
Opcode 0xEC000044
Extension Decimal Floating-Point
Registers Altered FPSCR, CR1

Operands

  • FRT
    Target FPR
  • FRA
    Source A
  • FRB
    Source B