dmul

Decimal Multiply

dmul FRT,FRA,FRB

Multiplies the contents of two DFP registers and places the result in another DFP register.

Encoding

Binary Layout

0

0:5

FRT

6:10

FRA

11:15

FRB

16:20

Rc

21:25

0

26

0

27:30

0

31

 

Format X-form

Opcode 0xEC000044

Extension Decimal Floating-Point

Operands

• FRT
  Target FPR
• FRA
  Source A
• FRB
  Source B

Example

dmul f1, f2, f3

// Financial Multiply.

Registers Altered

FPSCR, CR1

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Multiplies two 64-bit Decimal Floating Point (DFP) numbers held in FPRs and stores the result in another FPR. DFP multiplication preserves decimal precision required for financial calculations. The instruction can optionally update CR0 (via the dot form); FPSCR is always updated with exception flags and rounding information.

Operation

FPR[FRT] ← DFP_multiply(FPR[FRA], FPR[FRB])
FPSCR ← updated with exception flags
if Rc = 1 then CR0 ← condition_code(FPR[FRT])

Programming Note

dmul[q][.] are treated as Floating-Point instructions in terms of resource availability.