bcdutrunc.

Binary Coded Decimal Unsigned Truncate

bcdutrunc. VRT,VRA,VRB

Truncates the unsigned decimal value in VRB to a specified length and places it into VRT.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

21:29

321

Format VX-form

Opcode 0x10000541

Extension VMX (AltiVec)

Operands

VRT
Target Vector Register
VRA
Source Vector Register containing the length
VRB
Source Vector Register containing the unsigned decimal value

Example

bcdutrunc. v1, v2, v3

Registers Altered

CR6, CR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction truncates the unsigned decimal value in VSR[VRB+32] to the length specified by the integer value in bits 48:63 of VSR[VRA+32]. The result is placed into VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←0
do i = 0 to 31
    inv_flag ←inv_flag |
                (VSR[VRB+32].nibble[i] > 0x9)
end
length ←VSR[VRA+32].bit[48:63]
ox_flag ←0
eq_flag  ←(VSR[VRB+32].nibble[0:31] = 0)
gt_flag  ←(VSR[VRB+32].nibble[0:31] != 0)
if length < 32 then do
    do i = 0 to 31-length
        ox_flag ←1
        result.nibble[i] ←0b0000
    end
    if length > 0 then do
        do i = 32-length to 31
            result.nibble[i] ←VSR[VRB+32].nibble[i]
        end
    end
end
else result ←VSR[VRB+32]
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←0b0
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

Programming Note

The bcdutrunc. instruction is used to truncate an unsigned decimal value stored in a vector register. Ensure that the length specified in VSR[VRA+32] does not exceed 32 nibbles, as truncating beyond this will result in undefined behavior. The instruction sets various condition register bits (CR6) based on the operation's outcome, such as overflow and equality flags. Be cautious of invalid nibble values greater than 0x9, which can lead to incorrect results.