vaddsbs

Vector Add Signed Byte Saturate

vaddsbs vD, vA, vB

Adds 16 signed bytes with saturation (-128..127).

Encoding

Binary Layout

4

0:5

vD

6:10

vA

11:15

vB

16:20

768

21:31

 

Format VX-form

Opcode 0x10000300

Extension VMX (AltiVec)

Operands

• vD
  Target
• vA
  Src A
• vB
  Src B

Example

vaddsbs vd, va, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds each of sixteen signed 8-bit bytes in vA to the corresponding byte in vB, with saturation at the signed range [-128, 127]. Results below -128 are clamped to -128, and results above 127 are clamped to 127; no status flags are affected.

Operation

for i in 0 to 15 do
  sum ← SIGN_EXTEND(vA[i*8:(i+1)*8-1], 9) + SIGN_EXTEND(vB[i*8:(i+1)*8-1], 9)
  if sum > 127 then
    vD[i*8:(i+1)*8-1] ← 127
  else if sum < -128 then
    vD[i*8:(i+1)*8-1] ← -128
  else
    vD[i*8:(i+1)*8-1] ← sum[7:0]

Programming Note

The vaddsbs instruction is commonly used for vectorized addition of signed bytes, ensuring that results are clamped to the 8-bit signed integer range. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 16-byte vectors and processes each byte independently.