stxvpx

Store VSX Vector Paired Indexed X-form

stxvpx XSp,RA,RB

Stores a vector from two VSR registers into memory at the effective address.

Encoding

Binary Layout

0

0:5

Sp

6:10

SX

11:15

RA

16:20

RB

21:30

461

31

 

Format X-form

Opcode 0x7C00039A

Extension VSX

Operands

• XSp
  Index into VSR registers
• RA
  Base address register (GPR)
• RB
  Offset address register (GPR)

Example

stxvpx vs2, r4, r5

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction stores an octword (128 bits) of data from two VSR registers into memory. The data is stored in big-endian order if the system is configured for big-endian byte ordering, and little-endian order if the system is configured for little-endian byte ordering.

Operation

if MSR.VSX=0 then
    VSX_Unavailable()
EA ←((RA=0) ? 0 : GPR[RA]) + GPR[RB]
store_data.bit[0:127] ← VSR[32×SX+2×Sp]
store_data.bit[128:255] ← VSR[32×SX+2×Sp+1]
MEM(EA,32) ← store_data

Programming Note

For best performance, EA should be word-aligned.