stxvd2x

Store VSX Vector Doubleword*2 Indexed

stxvd2x XS, RA, RB

Stores a 128-bit VSX register to memory. Does NOT require alignment.

Encoding

Binary Layout

31

0:5

XS

6:10

RA

11:15

RB

16:20

972

21:30

1

31

 

Format XX1-form

Opcode 0x7C000798

Extension VSX

Operands

• XS
  Source VSR
• RA
  Base Register
• RB
  Index Register

Example

stxvd2x 32, r3, r4

// Unaligned 128-bit store.

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Stores a 128-bit VSX register to memory at the address computed from the base and index registers. The address is the sum of RA and RB (or 0 if RA = 0). Unlike some VSX store instructions, this instruction does not require natural alignment. No condition registers or status flags are affected.

Operation

EA ← (RA = 0) ? RB : (RA + RB)
[EA : EA+15] ← XS[0:127]

Programming Note

stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.