stxvd2x

Store VSX Vector Doubleword*2 Indexed

stxvd2x XS, RA, RB

Stores a 128-bit VSX register to memory. Does NOT require alignment.

Details

Stores a 128-bit VSX register to memory at the address computed from the base and index registers. The address is the sum of RA and RB (or 0 if RA = 0). Unlike some VSX store instructions, this instruction does not require natural alignment. No condition registers or status flags are affected.

Pseudocode Operation

EA ← (RA = 0) ? RB : (RA + RB)
[EA : EA+15] ← XS[0:127]

Programming Note

stxvd2x, stxvw4x, stxvh8x, stxvb16x, and stxvx exhibit identical behavior in Big-Endian mode.

Example

stxvd2x 32, r3, r4

// Unaligned 128-bit store.

Encoding

Binary Layout
31
0
XS
6
RA
11
RB
16
972
1
 
Format XX1-form
Opcode 0x7C000798
Extension VSX
Registers Altered MSR

Operands

  • XS
    Source VSR
  • RA
    Base Register
  • RB
    Index Register