xssubdp
VSX Scalar Subtract Double-Precision
Subtracts the contents of two double-precision floating-point registers and places the result in another register.
Details
The instruction subtracts the value of src2 (negated) from src1, producing a sum with unbounded range and precision. The sum is normalized and rounded to double-precision using the rounding mode specified by RN. The result is placed into doubleword element 0 of VSR[XT], and doubleword element 1 of VSR[XT] is set to 0.
Pseudocode Operation
if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src1 ← bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[0])
src2 ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_ADD(src1, bfp_NEGATE(src2))
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxisi_flag=1 then SetFX(FPSCR.VXISI)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxisi_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
FPSCR.FR ← inc_flag
FPSCR.FI ← xx_flag
else do
FPSCR.FR ← 0b0
FPSCR.FI ← 0b0
end
VSR[32×TX+T].dword[0] ← result
FPSCR.FPRF ← fprf_CLASS_BFP64(result)Programming Note
Let XT be the value 32×TX + T. Let XA be the value 32×AX + A. Let XB be the value 32×BX + B. Let src1 be the double-precision floating-point value in doubleword element 0 of VSR[XA]. Let src2 be the double-precision floating-point value in doubleword element 0 of VSR[XB].
Example
Encoding
Operands
-
XT
Target Vector-Scalar Register -
XA
Source Vector-Scalar Register -
XB
Source Vector-Scalar Register